FIG. 1 schematically illustrates a traditional SCR-based ESD protection device. As shown, the device in FIG. 1 includes substrate 101 with p-well region 103 and n-well region 105, and shallow trench isolation (STI) region 107 between well regions 103 and 105. As depicted, p-well region 103 includes P+ region 109 and N+ region 111 coupled to ground rail 113 (e.g., VSS), and n-well region 105 includes P+ region 115 and N+ region 117 coupled to I/O pad 119. In general, SCR-based ESD protection devices provide robust ESD performance and compact size. However, typical SCR-based ESD protection devices suffer from latch-up issues. For example, an ESD event (e.g., from I/O pad 119 to ground rail 113) may induce reverse breakdown with respect to n-well region 105 and substrate 101. If there is enough charge to maintain parasitic PNP and NPN structures, latch-up path 121 may occur, causing disruptions with regard to proper functioning of a circuit (e.g., that the SCR-based device is supposed to protect) or even destruction of the circuit due to excess current.
FIG. 2 schematically illustrates characteristics of a traditional SCR-based ESD protection device under an ESD condition. As shown, in diagram 201, once the trigger voltage (Vt) is reached, the SCR-based ESD protection device will snapback to the holding voltage (Vh) (e.g., for maintaining the parasitic PNP and NPN structures). In addition, as depicted, a traditional SCR-based ESD protection device has a high trigger voltage (e.g., Vt1˜10 V for logic process), a low trigger current (e.g., It1˜mA), and a low holding voltage (e.g., Vh˜2 V). Consequently, a traditional SCR-based ESD protection device fails to adequately provide protection from latch-up events (e.g., transient ESD-induced latch-ups, static latch-up testing, etc.). Although latch-up issues may be reduced by increasing the p-n junction space of the SCR and cascading the SCR to increase the holding voltage (Vh) of the SCR, such an approach consumes substantially more device/chip area than necessary, resulting in the need for larger device/chip size.
A need therefore exists for an efficient latch-up robust SCR-based device, and enabling methodology.